1. Technical Field
The present invention relates to a test apparatus, an adjustment method, and a recording medium. More particularly, the present invention relates to a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal for outputting a clock signal showing the timing at which data signals output from the plurality of data terminals should be acquired, and an adjustment method and a recording medium therefor.
2. Related Art
There is known a device (a source synchronous device) including a plurality of data terminals and a clock output terminal for outputting a clock signal showing the timing at which data signals output from the plurality of data terminals should be acquired. A test apparatus that tests a device under test having a high-speed serial interface operating in a clock embedding method is known as disclosed, for example, in Japanese Patent Application Publication No. 2005-285160.
Meanwhile, according to a conventional test apparatus, since a delay amount of a transmission route of a data signal and a delay amount of a transmission route of a clock signal are different between pins, it has been difficult to simultaneously acquire a plurality of data signals using a clock signal output from a source synchronous device as a standard and test the plurality of data signals in parallel.